The present invention relates to nanowire field effect transistor (FET) devices and more particularly, to techniques for fabricating a nanowire FET device using a replacement gate fin first, wire last process in order to form gate all around devices.
In its basic form, a field-effect transistor (FET) includes a source region, a drain region and a channel between the source and drain regions. A gate regulates electron flow through the channel that is between the source and drain regions.
Due to their superior electrostatics, gate all around nanowire channel field effect transistors (e.g., nanowire FETs) are expected to enable density scaling beyond current planar complementary metal oxide semiconductor (CMOS) technology. There are, however, notable challenges related to fabricating gate all around nanowire FETs, especially at scaled dimensions. For instance, in the conventional art, one difficulty with fabricating nanowire FETs is preserving the nanowire from damage during the fabrication process. Additionally, in a gate-first process flow, the gate material needs to be removed beneath the source/drain region of the device by some undercut method, which using conventional methods may also result in critical dimension loss of the gate line itself, potentially harming process and device scalability. Also, in wire-before-gate, gate-first or replacement gate processes, the nanowire must be suspended using a landing pad region, which may in turn harm layout efficiency.